1. Field of the Invention
The present invention generally relates to serial data bus communication systems. More particularly, the present invention relates to an adaptive data separator capable of recovering encoded information from an encoded signal which may have been subject to systematic distortion of signal edges.
2. Description of Related Art
Computer systems incorporate many components, each of which must generally be capable of either conveying or receiving information from other parts of the system. Numerous data communications schemes have been developed for the exchange of data between the various components and peripherals implemented in a given computer system.
One of the prominent methods of data communications within computer systems is the use of a serial data bus for transmitting encoded information. If a single data line is used for transmission, then usually the clock information and data information are combined. A variety of conventional encoding schemes are employed to send combined clock and data transmissions over a single data line. Examples are Manchester, 4B5B and 8B10B. Transmissions encoded in, for example, binary 4B5B encode 4 bits of data in 5 NRZ binary symbols. The purpose of the encoding is to guarantee both a dc balanced signal and enough transitions for clock extraction circuits to be able to extract the clock signal. A typical sequence of symbols within a transmitted signal is shown in FIG. 1. As can be seen, each symbol of the transmitted signal fills a bit cell. For 40 megabit 4B5B data, the symbol rate is 50 Mbaud and the bit cell is 20 nanoseconds. Co-pending patent application entitled "Delay Line Separator for Data Bus," application Ser. No. 08/004,441, filed Jan. 19, 1993, invented by Roger Van Brunt and Florin Oprescu and assigned to the assignee of the present invention describes a method and apparatus for extracting clock information from combined clock/data packets propagated according to the IEEE 1394 standard.
Data transmission systems often introduce systematic distortion of signal edges with the rising edge delayed longer than the falling edge or vice versa. If this distortion is too large, data recovery using conventional methods becomes impossible since those methods depend on the symmetry of the rising and falling edge distortion. A number of different types of noise or distortion can affect a packet as it is transmitted over a serial data bus. Of particular interest to short range, high speed data burst transmissions is a systematic distortion which uniformly varies the duty cycle of the symbols within the data packet. Referring again to FIG. 1, a symbol within a transmitted signal is bounded by a rising edge and sharp falling edge and has a width equal to the bit cell, typically 20 nanoseconds for 50 Mbaud 4B5B. However, during transmission of the packet, a pulse corresponding to a single symbol is broadened or narrowed, such that the time between a rising edge and a succeeding falling edge is increased or decreased. Such a systematic error is represented in FIG. 1 by the received signal, which includes rising edges advanced by one or two nanoseconds and falling edges delayed by one or two nanoseconds. With such distortion, each high symbol is broadened and spacing between high symbols is decreased. Thus, whereas the bit cell width of the transmitted signal is easily determined from the time between rising and falling edges, the bit cell width cannot be easily determined from the time between rising and falling edges of the received signal. Although shown as broadening each signal, systematic distortion of the kind described can also narrow each symbol, thus broadening or narrowing of symbols can be quite significant, often resulting in an initial 20 nanosecond symbol being expanded to a width of 30 nanoseconds or narrowed to a width of 10 nanoseconds.
A unique feature of the systematic distortion is that the distance between successive rising edges is unaffected by the distortion. This is true because the source of the distortion affects each symbol pulse in the same manner and by the same amount such that all rising edges are advanced or delayed by a certain amount and all falling edges are advanced or delayed by a certain amount. Such systematic distortion is commonly referred to as duty-cycle distortion and may arise from a rise/fall time mismatch or from offsets in the receiver. Other types of distortion, which do not preserve the time between successive rising edges, include external noise, transient noise and inter-symbol interference. However, during transmission and reception of the packet, the symbol pulse widths are distorted such that high symbol pulse widths are increased (decreased) while low symbol pulse widths are correspondingly decreased (increased) by the same amount. This distortion may vary from packet to packet but does not vary during a packet transmission. The amount of broadening and narrowing of the symbols can be quite significant, often resulting in an initial 20 nanosecond symbol bit cell being expanded to a width of 30 nanoseconds while the opposite value symbol is decreased to 10 nanoseconds.
Heretofore, no effective techniques have been developed which allow the accurate sampling of data information from a high speed clock/data burst in the presence of significant duty-cycle distortion. Techniques which have addressed the problem are either not sufficiently effective in accurately determining the data signal or are complex, thus rendering the system expensive.